In recent years, an active-matrix-type image display device (display device) including a thin film transistor (TFT) has come to the fore as a display device ensuring high picture quality.
The following will explain an active-matrix-type image display device with reference to FIG. 20.
As shown in FIG. 20, an active-matrix-type display device includes a pixel array 102 a plurality of pixels 108 aligned in a matrix manner, a data signal line driving circuit 103 for driving data signal lines s1 of the pixel array 102, a scanning signal line driving circuit 104 for driving scanning signal lines g1 of the pixel array 102, a power source circuit 105 for supplying power to the respective driving circuits 103 and 104, and a control circuit 106 for supplying a control signal to the respective driving circuits 103 and 104.
In addition to the plurality of pixels 108, the pixel array 102 includes a plurality of data signal lines s1 and a plurality of scanning signal lines g1, which intersect the data signal lines s1, respectively. The pixel 108 is provided for each pair of the respective data signal lines s1 and the respective scanning signal lines g1.
The control circuit 106 outputs an image signal dat indicating an image to be displayed in the pixel array 102. The image signal dat is constituted of image data showing display condition for the respective pixels 108 in the target image and transmitted in a time divisional manner. The control circuit 106 outputs a clock signal sck and a start pulse signal ssp to the data signal line driving circuit 103 as timing signals with the image signal dat, so as to allow the image signal dat to be appropriately displayed in the pixel array 102, and also outputs the clock signal gck and the start pulse signal gsp to the scanning signal line driving circuit 104.
The scanning signal line driving circuit 104 sequentially selects the plurality of scanning signal lines g1 in synchronism with a timing signal, such as the clock signal gck. Further, the data signal line driving circuit 103 operates in synchronism with a timing signal, such as the clock signal sck, and specifies appropriate timings to be corresponding to the respective data signal lines s1. Further, the data signal line driving circuit 103 samples the image signal dat at the specified timings, and write the resulting signals to the respective data signal lines s1 as a result of sampling.
Meanwhile, while the corresponding scanning signal line g1 is selected, the respective pixels 108 control brightness corresponding to the data outputted to the corresponding data signal line s1. Consequently, the pixel array 102 displays an image indicated by the image signal dat.
Next, the following will explain a circuit structure of the data signal line driving circuit. The structure of the data signal line driving circuit differs depending on whether the image signal dat is an analog signal or a digital signal; however, its common structure is made up of a shift register and a plurality of waveform processing circuits (processing circuit) for processing selection signals which are sequentially supplied from the respective stages of the shift register.
The shift register is constituted of a plurality of flip-flops (unit circuit), which are sequentially connected in a form of cascade connection, so as to output a supplied pulse according to a separately supplied clock signal. Each of the flip-flops is provided as an output stage of the shift register. When a start pulse signal (input signal) is supplied to the shift register, the start pulse signal is sequentially outputted starting from the first flip-flop of the input side, through the respective stages of the flip-flops at the same timing as the clock signal.
FIG. 17 shows a conventional layout of a data signal line driving circuit including one system shift register sr.
As shown in the figure, the flip-flops F/F are individually provided for each alignment of the data signal lines s1. In this structure, the flip-flops F/F (1), F/F (2), . . . F/F (n) are linearly disposed and sequentially connected in a form of cascade connection, corresponding to the n data signal lines s1. More specifically, the respective flip-flops F/F are simultaneously supplied with the clock signal (control signal) sck, and the input terminal IN of the first-stage flip-flop F/F (1) is supplied with the start pulse (control signal) ssp, and output of the output terminal OUT of the flip-flop F/F (1) is supplied to the input terminal IN of the next-stage flip-flop F/F (2) and the input terminal IN of the waveform processing circuit WR (1). Likewise, output of the output terminal OUT of the flip-flop F/F (2) is supplied to the input terminal IN of the next-stage flip-flop F/F (3) and the input terminal IN of the waveform processing circuit WR (2). In the same manner, the signal is supplied to the remaining flip-flops and the waveform processing circuits.
The plurality of waveform processing circuits WR (1), WR (2), . . . WR (n), which are supplied with output signals of the respective flip-flops F/F of the shift register, are provided along the data signal line s1 of the corresponding flip-flop, in other words, in a portion closer to the starting side of the data signal line s1.
Each flip-flop F/F and the corresponding waveform processing circuit WR constitute a circuit block for driving one data signal line s1. Note that, in the present specification, the horizontal direction refers to the alignment direction of the data signal lines s1, i.e., the direction along the scanning signal line g1, and the vertical direction refers to the orthogonal direction, i.e., the direction along the data signal line s1.
Some of the data signal line driving circuit include a plurality of shift registers, each of which has a less number of output stages, i.e., a less number of flip-flops F/F. In the present specification, a shift register block refers to a group of shift registers including a required number of output stages regardless of the number of systems of shift register.
The shift register in multiple-systems is aimed at reduction of driving frequency of the driving circuit. For example, a two-system shift register can reduce the driving frequency to ½.
FIG. 18 shows a conventional layout of the data signal line driving circuit made up of a two-system shift register. As shown in the figure, the first system shift register sr1 is made up of a flip-flop F/F1(1), F/F1(2), . . . F/F1(m), and supplied with the clock signal sck1 and the start pulse ssp1 as control signals; and the second system shift register sr1 is made up of a flip-flop F/F2(1), F/F2(2), . . . F/F2(m), and supplied with the clock signal sck2 and the start pulse ssp2 as control signals. The first and second systems are provided to be in parallel with each other in the vertical direction.
Further, a plurality of waveform processing circuit WR1(1) through WR1(m), which are respectively supplier with outputs of the flip-flops F/F1(1) through F/F1(m) constituting the first system shift register sr1, are provided between the first system shift register sr1 and the second system shift register sr2. Likewise, a plurality of waveform processing circuit WR2(1) through WR2(m), which are respectively supplied with outputs of the flip-flops F/F2(1) through F/F2(m) constituting the second system shift register sr2, are provided in parallel with the second system shift register sr2.
Further, apart from reduction of driving frequency, such a data signal line driving circuit including multiple-systems of shift register is aimed at provision of a redundant shift register in addition to the regular shift registers, as a redundant circuit to be used in case of defect (For example, refer to the specification of U.S. Pat. No. 5,889,504 (Japanese Laid-Open Patent Application Tokukaihei 08-212793/1996 (published on Aug. 20, 1996))).
Further, some of conventional active-matrix-type display devices adopt a driving method in which an image signal is divided to be separate image signals, which are simultaneously sampled when the signals are supplied to a plurality of image signal lines (For example, refer to Japanese Laid-Open Patent Application Tokukaihei 11-24632/1999 (published on Jan. 29, 1999)).
With reference to FIG. 19, the following will explain this driving method, which is commonly known as a multiple-system operation. As shown in the figure, the image signal dat is not divided in an arrangement not using the multiple-system operation, and therefore only one circuit block is required for the pixels of Red (R), Green (G) and Blue (B), since these three color pixels are simultaneously driven as one group by output of the one circuit block, which is constituted of a flip-flop F/F and a waveform processing circuit WR.
On the other hand, in the two-system operation in which the image signal dat is divided into two pieces, the number of image signal lines doubles compared with the arrangement which does not use the multiple-system operation. However, the two data signal lines SL, each of which drives two groups of R, G and B pixels, are driven by the same timing. Therefore, in this two-system operation, only one circuit block is required for two groups of pixels.
Accordingly, in a four-system operation, four data signal lines SL individually drive four groups of R, G and B pixels at the same timing using only one circuit block. Likewise, an eight-system operation requires one circuit block for eight groups of pixels.
By thus performing such a multiple-system operation, the number of image signal lines increases so as to carry the divided signal; however, the increased number of data signal lines can be driven as one group by only one circuit block. Thus, the area occupied by one circuit block, which is an area extended in the horizontal direction and restricted by the pixel pitch, can be widened, and the sampling frequency can be reduced.
As has been described, a data signal line driving circuit using such a multiple-system operation, in which the image signal is divided, is becoming more common. The simultaneous operation in which a plurality of data signal lines SL are driven at the same time offers a wider area for the circuit block in the horizontal direction. As can be seen in FIG. 19, the area becomes respectively twice, four times, and eight times as large as the arrangement not using the multiple-system operation, in a two-system operation, in a four-system operation, and in an eight-system operation.
However, in such a conventional data signal line driving circuit, the respective waveform processing circuits WR are positioned closer to the output side (refer to FIG. 17) of the shift register sr, i.e., the waveform processing circuits WR are extended in the vertical direction. With this structure, the area widened in the horizontal direction due to multiple-system operation is effectively not used.
Further, in the multiple-systems of shift register of FIG. 18 with the shift registers sr1 and sr2 adjacently disposed in the vertical direction, the respective systems have different distances from the data signal lines SL. This causes variation of delay time of the output of the shift register, thus degrading display quality.
Such variation of delay time can be solved by processing the clock signal sck etc. supplied to the shift registers sr1 and sr2. However, the processing induces unwanted increase of circuit scale, since the processing of signal requires more complicated circuit structure.